1. Field of the Invention
The invention relates to programmable devices, more particularly to a method and apparatus for effectively re-downloading data to a Field Programmable Gate Array (FPGA), which can easily re-configure the FPGA to increase convenience and speed in R&D and upgrade, and further save developing costs.
2. Description of the Related Art
Field Programmable Gate Arrays (FPGAs) are frequently used in multimedia, workstations, communications, networks and other applications. The appealing characteristics of FPGAs are speeds approaching those of an integrated circuit (IC) and programmability for design simulation and trial-and-error flexibility.
FPGAs are essentially configured in SRAM based mode and Anti-fuse-based mode. The SRAM based mode is widely used for IC design mode in the aforementioned applications.
The advantages for the SRAM based mode include reprogrammability, low power consumption and in-circuit configurability. However, this mode typically downloads configuration data from a host system such as a computer or workstation using an FPGA interface cable. As such, the performance for such a mode depends on joint download circuits.
FIG. 1 is a schematic diagram of an internal circuit of a typical Field Programmable Gate Array (FPGA). As shown in FIG. 1, existing download circuits generally use a Non-Volatile Random Access Memory (NVRAM) to store configuration data codes required by design circuit in the FPGA. However, such an application requires a control access circuit 16 with two functions: one for downloading external update configuration data codes to NVRAM 14 (namely Write-to-NVRAM function) and the other for writing configuration data codes in NVRAM 14 to FPGA 12 (namely Write-to-FPGA function). The cited circuits are normally integrated into a printed circuit board (PCB) 10. Thus, a user can easily change the configuration circuit in FPGA when performing R&D. When initialing mass-production, configuration data codes are directly downloaded without changing PCB circuitry. However, after mass-production is complete, the Write-to-NVRAM function is not needed. Accordingly, the circuit 16 including functions of downloading configuration data codes to NVRAM 14 and reading configuration data codes from NVRAM 14 is set aside, wasting resources. Additionally, in some products separating the two functions, when initialing mass-production, only the Write-to-FPGA function is left with operating codes. As such, the circuit 16 is removed to thus eliminate resource waste. However, as updates required by FPGA must extract NVRAM and then write new configuration data codes by existing burner or other devices, thus causing inconvenience in R&D and difficulty in upgrade.